The present invention relates generally to memory devices, and particularly to memory writing schemes.
In electronic memory systems, it is often desirable to allow writing to multiple rows in a memory device. However, when write word widths are not a power of two times the read word width, address holes in the read address space will result. In previous solutions to this problem, the memory array was made larger so as to end up with a power of two for the column decode in order to eliminate holes in the read address space. This solution is disadvantageous since it requires the memory area to be larger for a given storage capacity and can require overhead external to the memory area in order to account for address holes.
The present invention allows writing to multiple rows in a memory device that eliminates holes in the address space arising from writing in word widths that are not a power of two times the read word width. In one embodiment, the present invention includes first and second memory blocks, a circuit for determining whether an address of a write word to be written to either of the first and second memory blocks is even or odd, and a second circuit for writing a first group of bits in the write word to the first memory block and a second group of bits in the write word to the second memory block when the address of the word is even, and for writing a first group of bits in the write word to the second memory block and second group of bits in the write word to the first memory block when the address of the write word is odd, wherein address holes in read address space of said first and second information storing means are reduced or eliminated.